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datasheet 1-to-8 differential to universal output clock divider/fanout buffer IDT8T79S818I-08 idt8t79s818a-08nlgi revision a july 11, 2013 1 ?2013 integrated device technology, inc. general description the IDT8T79S818I-08 is a high performance, 1-to-8, differential input to universal output clock divider and fanout buffer. the device is designed for frequency-division and signal fanout of high-frequency clock signals in applications requiring four different output frequencies generated simultaneously. each bank of two outputs has a selectable divider value of 1 through 6 and 8. the IDT8T79S818I-08 is optimized for 3. 3v and 2.5v supply voltages and a temperature range of -40c to 85c. the device is packaged in a space-saving 32 lead vfqfn package. features ? four banks of two low skew outputs ? selectable bank output divider values: 1 through 6 and 8 ? one differential pclk, npclk input ? pclk, npclk input pair can accept the following differential input levels: lvpecl, lvds levels ? maximum input frequency: 1.5ghz ? lvcmos control inputs ? qxx 1 edge aligned to qxx n edge ? individual output divider control via serial interface ? individual output enable/disable control via serial interface ? individual output type control, lvds or lvpecl, via serial interface ? 2.375v to 3.465v supply voltage operation ? -40c to 85c ambient operating temperature ? lead-free (rohs 6) packaging qa0 nqa0 qa1 nqa1 qb0 nqb0 qb1 nqb1 qc0 nqc0 qc1 nqc1 qd0 nqd0 qd1 nqd1 dividers rst divider select, output type and output enable logic pclk npclk oe nrst miso sclk sdata vcc vee vee vee vee pullup/pulldown pulldown pulldown pulldown pulldown pullup pwr_sel le vee vcc vee pulldown pulldown vee 7 12 10 IDT8T79S818I-08 32 lead vfqfn 5mm x 5mm x 0.925mm pad size 3.15mm x 3.15mm nl package top view 25 26 27 28 29 30 31 1 2 3 4 5 6 7 16 15 14 13 12 11 10 24 23 22 21 20 19 18 v cc v ee nqa1 qa1 nqa0 qa0 v cc sdata 32 8 9 17 v cc v ee qd0 nqd0 qd1 nqd1 v cc pwr_sel s c l k m i s o n r s t p c l k n p c l k o e v c c l e q b o n q b 0 q b 1 n q b 1 q c 0 n q c 0 q c 1 n q c 1 block diagram pin assignment
idt8t79s818a-08nlgi revision b july 11, 2013 2 ?2013 integrated device technology, inc. IDT8T79S818I-08 data sheet 1-to-8 differential to universal output, clock divider/fanout buffer pin description and characteristic tables table 1. pin descriptions note: pullup and pulldown refer to internal input resistors. see ?table 2. pin characteristics? for typical values. table 2. pin characteristics number name type description 1 sclk input pulldown serial control port mode data input. lvcmos/lvttl interface levels. 2 miso output serial control port mode data output. lvcmos/lvttl interface levels. 3 nrst input pullup frequency divider reset. when the nrst is released (rising edge), the divided clock outputs are activated and will tran sition to a high state simultaneously. see also timing diagram. lvcmos/lvttl interface levels ( ?figure 1. timing diagram? ). 4 pclk input pulldown non-inverting differential clock input. 5 npclk input pullup / pulldown inverting differential clock input. v cc / 2 by default when left floating. 6 oe input pulldown default output disable. lvcmos /lvttl interface levels. see ?table 3b. oe truth table? . 7, 10, 16, 25, 31 v cc power power supply voltage pin. 8 le input pulldown serial control port mode load enable. latches data when the pin gets a high level. outputs are disabled when le is low. lvcmos/lvttl interface levels. 9 pwr_sel pulldown power supply selection. see ?table 3a. pwr_sel truth table? . 11, 12 nqd1, qd1 output differential output pair bank d, output 1. lvpecl or lvds interface levels. 13, 14 nqd0, qd0 output differential output pair bank d, output 0. lvpecl or lvds interface levels. 15, 26 v ee power negative power supply pins. 17, 18 nqc1, qc1 output differential output pair bank c, output 1. lvpecl or lvds interface levels. 19, 20 nqc0, qc0 output differential output pair bank c, output 0. lvpecl or lvds interface levels. 21, 22 nqb1, qb1 output differential output pair bank b, output 1. lvpecl or lvds interface levels. 23, 24 nqb0, qb0 output differential output pair bank b, output 0. lvpecl or lvds interface levels. 27, 28 nqa1, qa1 output differential output pair bank a, output 1. lvpecl or lvds interface levels. 29, 30 nqa0, qa0 output differential output pair bank a, output 0. lvpecl or lvds interface levels. 32 sdata input pulldown serial control port mode data inpu t. lvcmos/lvttl interface levels. symbol parameter test conditio ns minimum typical maximum units c in input capacitance 2pf r pullup input pullup resistor 51 k ? r pulldown input pulldown resistor 51 k ? r out output impedance miso v cc = 3.3v 125 ? v cc = 2.5v 145 ?
idt8t79s818a-08nlgi revision b july 11, 2013 3 ?2013 integrated device technology, inc. IDT8T79S818I-08 data sheet 1-to-8 differential to universal output, clock divider/fanout buffer function tables table 3a. pwr_sel truth table table 3b. oe truth table pwr_sel function l (connect to v ee ) 2.5v power supply h (connect to v cc ) 3.3v power supply oe function l (default) all outputs disabled (low/high static mode), rega rdless of individual oe registers set by serial interface. h outputs enabled according to individual oe registers set by serial interface (see ?table 3e. configuration ta b l e ? ).
idt8t79s818a-08nlgi revision b july 11, 2013 4 ?2013 integrated device technology, inc. IDT8T79S818I-08 data sheet 1-to-8 differential to universal output, clock divider/fanout buffer output type control and start-up status two output types are available: lvds and lvpecl. the part features four modes of output type controls, see table 3c. disabled outputs are in static low/ high lvds mode. at start-up, all outputs are disabled (i.e. in static low/high lvds mode) until the part has been configured. a global hard ware output enable (oe pin #6) enables or disables all outputs at once. the global hardware oe has priority over serial interface configuration. table 3c. output type control frequency divider each output bank can be individually set to output an integer division of the input frequency. factors of 1, 2, 3, 4, 5, 6 and 8 are available and are programmed by a serial interface. the nrst pin resets the dividers. when the nrst pin is released, all ou tput dividers are activated and will transition to a high state simultaneously. qxn (/ 1) qxn (/ 2) qxn (/ 3) qxn (/ 4) qxn (/ 5) qxn (/ 6) qxn (/ 8) figure 1. timing diagram control bits output configuration d2 d1 low low 8 lvds outputs high high 8 lvpecl outputs high low 2 lvds (qax) + 6 lvpecl (qbx, qcx, qdx) outputs low high 2 lvpecl (qax) + 6 lvds (qbx, qcx, qdx) outputs
idt8t79s818a-08nlgi revision b july 11, 2013 5 ?2013 integrated device technology, inc. IDT8T79S818I-08 data sheet 1-to-8 differential to universal output, clock divider/fanout buffer serial interface configuration of the IDT8T79S818I-08 is achieved by writing 22 configuration bits over serial interface. all 22 bits have to be written in sequence. after writing the 22 configuration bits, the le pin must remain at high le vel for outputs to toggle. d22 d21 d3 d2 d1 miso d22 d21 d3 d2 d1 sclk sdata le t sl t s t h t he t hi t lo t delay t sh figure 2. serial interface timing diagram for write and read access table 3d. timing ac characteristics note: electrical parameters are guaranteed over the specified ambient operating temperature rang e, which is established when th e device is mounted in a test socket with maintained transverse airflow greate r than 500 lfpm. the device will meet specifications after th ermal equilibrium has been reached under these conditions. symbol parameter test conditions minimum typical maximum units t s data to clock setup time 10 ns t h data to clock hold time 10 ns t he clock to le hold time 10 ns t hi clock high duration 25 ns t lo clock low duration 25 ns t sl le to clock setup time 10 ns t sh le to sclk setup time 10 ns t delay clock to miso delay time 10 ns
idt8t79s818a-08nlgi revision b july 11, 2013 6 ?2013 integrated device technology, inc. IDT8T79S818I-08 data sheet 1-to-8 differential to universal output, clock divider/fanout buffer table 3e. configuration table table 3f. divider setting truth table bit name function truth table d22 sd0 output bank d, divider factor setting bit 0 see ?table 3f. divider setting truth table? d21 sd1 output bank d, divider factor setting bit 1 d20 sd2 output bank d, divider factor setting bit 2 d19 sc0 output bank c, divider factor setting bit 0 d18 sc1 output bank c, divider factor setting bit 1 d17 sc2 output bank c, divider factor setting bit 2 d16 sb0 output bank b, divider factor setting bit 0 d15 sb1 output bank b, divider factor setting bit 1 d14 sb2 output bank b, divider factor setting bit 2 d13 sa0 output bank a, divider factor setting bit 0 d12 sa1 output bank a, divider factor setting bit 1 d11 sa2 output bank a, divider factor setting bit 2 d10 oed1 output enable qd1 low: disabled high: enabled d9 oed0 output enable qd0 d8 oec1 output enable qc1 d7 oec0 output enable qc0 d6 oeb1 output enable qb1 d5 oeb0 output enable qb0 d4 oea1 output enable qa1 d3 oea0 output enable qa0 d2 ot1 banks qb, qc, qd output type low: lvds high: lvpecl d1 ot0 bank qa output type sd2 sc2 sb2 sa2 sd1 sc1 sb1 sa1 sd0 sc0 sb0 sa0 divide ratio lll 1 llh 2 lhl 3 lhh 4 hll 5 hlh 6 h h l reserved hhh 8
idt8t79s818a-08nlgi revision b july 11, 2013 7 ?2013 integrated device technology, inc. IDT8T79S818I-08 data sheet 1-to-8 differential to universal output, clock divider/fanout buffer absolute maximum ratings note: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these ratings are stress specifications only. functional operati on of product at these conditions or any conditions beyond those listed in the dc characteristics or ac characteristics is not implied. exposure to absolute maximum rating conditions for extended periods may affect product reliability. supply voltage, v cc 4.6v inputs, v i -0.5v to v cc + 0.5v outputs, v o (lvcmos) -0.5v to v cc + 0.5v outputs, i o (lvpecl) continuous current surge current outputs, i o (lvds) continuous current surge current 50ma 100ma 10ma 15ma package thermal impedance, t ja 48.9 q c/w (0 mps) storage temperature, t stg -65 q c to 150 qc dc electrical characteristics table 4a. power supply dc characteristics, v cc = 3.3v 5%, v ee = 0v, t a = -40c to 85c with airflow table 4b. power supply dc characteristics, v cc = 2.5v 5%, v ee = 0v, t a = -40c to 85c item rating symbol parameter test conditio ns minimum typical maximum units v cc power supply voltage 3.135 3.3 3.465 v i ee power supply current lvpecl 147 175 ma i cc power supply current lvds 237 284 ma symbol parameter test conditio ns minimum typical maximum units v cc power supply voltage 2.375 2.5 2.625 v i ee power supply current lvpecl 130 165 ma i cc power supply current lvds 230 272 ma
idt8t79s818a-08nlgi revision b july 11, 2013 8 ?2013 integrated device technology, inc. IDT8T79S818I-08 data sheet 1-to-8 differential to universal output, clock divider/fanout buffer table 4c. lvcmos/lvttl dc characteristics, v cc = 3.3v 5%, v ee = 0v, t a = -40c to 85c with airflow table 4d. differential input dc characteristics, v cc = 3.3v 5% or 2.5v 5%, v ee = 0v, t a = -40c to 85c with airflow note 1: v il should not be less than -0.3v. ? note 2: common mode input voltage is defined as crosspoint. table 4e. lvpecl dc characteristics, v cc = 3.3v 5%, v ee = 0v, t a = -40c to 85c with airflow note 1: outputs terminated with 50 ? to v cc ? 2v. symbol parameter test conditio ns minimum typical maximum units v ih input high voltage v cc = 3.3v 2.2 v cc + 0.3 v v cc = 2.5v 1.7 v cc + 0.3 v v il input low voltage v cc = 3.3v -0.3 0.8 v v cc = 2.5v -0.3 0.7 v i ih input high current nrst v cc = v in = 3.465v or 2.625v 10 a oe, le, pwr_sel, ? sclk, sdata v cc = v in = 3.465v or 2.625v 150 a i il input low current nrst v cc = 3.465v or 2.625v, v in = 0v -150 a oe, le, pwr_sel, ? sclk, sdata v cc = 3.465v or 2.625v, v in = 0v -10 a v oh output high voltage miso v cc = 3.465v i oh = -1ma 2.6 v v cc = 2.625v i oh = -1ma 1.8 v v ol output low voltage miso v cc = 3.465v or 2.625v i ol = 1ma 0.5 v symbol parameter test conditio ns minimum typical maximum units i ih input high current pclk, npclk v cc = v in = 3.465v or 2.625v 150 a i il input low current pclk v cc = 3.465v or 2.625v, v in = 0v -10 a npclk v cc = 3.465v or 2.625v, v in = 0v -150 a v pp peak-to-peak voltage; note 1 0.15 1.3 v v cmr common mode input voltage; note 1, 2 v ee + 1 v cc ? 0.5 v symbol parameter test conditio ns minimum typical maximum units v oh output high voltage; note 1 v cc ? 1.3 v cc ? 0.75 v v ol output low voltage; note 1 v cc ? 2.0 v cc ? 1.6 v v swing peak-to-peak output voltage swing 0.6 1.0 v
idt8t79s818a-08nlgi revision b july 11, 2013 9 ?2013 integrated device technology, inc. IDT8T79S818I-08 data sheet 1-to-8 differential to universal output, clock divider/fanout buffer table 4f. lvpecl dc characteristics, v cc = 2.5v 5%, v ee = 0v, t a = -40c to 85c note 1: outputs terminated with 50 ? to v cc ? 2v table 4g. lvds dc characteristics, v cc = 3.3v 5%, v ee = 0v, t a = -40c to 85cwith airflow table 4h. lvds dc characteristics, v cc = 2.5v 5%, v ee = 0v, t a = -40c to 85c symbol parameter test conditio ns minimum typical maximum units v oh output high voltage; note 1 v cc ? 1.3 v cc ? 0.75 v v ol output low voltage; note 1 v cc ? 2.0 v cc ? 1.6 v v swing peak-to-peak output voltage swing 0.6 1.0 v symbol parameter test conditio ns minimum typical maximum units v od differential output voltage 247 454 mv ? v od v od magnitude change 50 mv v os offset voltage 1.125 1.45 v ? v os v os magnitude change 50 mv symbol parameter test conditio ns minimum typical maximum units v od differential output voltage 247 454 mv ? v od v od magnitude change 50 mv v os offset voltage 1.125 1.45 v ? v os v os magnitude change 50 mv
idt8t79s818a-08nlgi revision b july 11, 2013 10 ?2013 integrated device technology, inc. IDT8T79S818I-08 data sheet 1-to-8 differential to universal output, clock divider/fanout buffer ac electrical characteristics table 5. ac characteristics, v cc = 3.3v 5% or 2.5v 5%, v ee = 0v, t a = -40c to 85c with airflow note: electrical parameters are guaranteed over the specified am bient operating temperature rang e, which is established when th e device is mounted in a test socket with maintained transverse airflow grea ter than 500 lfpm. the device will meet specifications after th ermal equilibrium has been reached under these conditions. ? note 1: this parameter is defined in accordance with jedec standard 65. ? note 2: defined as skew between outputs at the same supply volt age and with equal load conditions. measured at the differential cross points. ? note 3: defined as skew within a bank of outputs at the same voltage and with equal load conditions. ? note 4: defined as skew between outputs on different devices o perating at the same supply voltage, same frequency, same tempera ture and with equal load conditions. using the same type of inputs on each device, the outputs are measured at the differential cross po ints. ? note 5: measured from the differential input cro ssing point to the differential output crossing point. symbol parameter test conditio ns minimum typical maximum units f in input frequency pclk, npclk 1.5 ghz f out output frequency f in = 1500mhz, qx = 1 1500 mhz f in = 1500mhz, qx = 2 750 mhz f in = 1500mhz, qx = 3 500 mhz f in = 1500mhz, qx = 4 375 mhz f in = 1500mhz, qx = 5 300 mhz f in = 1500mhz, qx = 6 250 mhz f in = 1500mhz, qx = 8 187.5 mhz t pd propagation delay; note 5 all outputs operating at the same frequency 0.57 0.8 1 ns t sk (o) output skew; note 1, 2 all outputs operating at the same frequency 80 ps t sk (b) bank skew; note 1, 3 outputs within each bank operating at the same frequency 55 ps t sk (pp) part-to-part skew; note 1, 4 450 ps t r / t f output rise/fall time lvpecl 20% to 80% 50 300 ps lvds 20% to 80% 50 300 ps odc output duty cycle 40 60 %
idt8t79s818a-08nlgi revision b july 11, 2013 11 ?2013 integrated device technology, inc. IDT8T79S818I-08 data sheet 1-to-8 differential to universal output, clock divider/fanout buffer parameter measurement information 3.3v lvpecl output load test circuit 3.3v lvds output load test circuit differential input levels 2.5v lvpecl output load test circuit 2.5v lvds output load test circuit propagation delay scope qx nqx v ee v cc 2v -1.3v 0.165v v cc v cc v ee npclk pclk scope qx nqx v ee -0.5v 0.125v v cc 2v v cc t pd npclk pclk nqxx qxx
idt8t79s818a-08nlgi revision b july 11, 2013 12 ?2013 integrated device technology, inc. IDT8T79S818I-08 data sheet 1-to-8 differential to universal output, clock divider/fanout buffer parameter measurement in formation, continued output skew part-to-part skew lvpecl output rise/fall time bank skew lvds output rise/fall time output duty cycle/pulse width/period where x = bank a, b, c or d nqxx qxx nqxy qxy t sk(pp) part 1 part 2 nqxx qxx nqxy qxy where x = bank a, b, c or d nqxx qxx where x = bank a, b, c or d t sk(b) where x = bank a, b, c or d nqxx qxx nqxy qxy 20% 80% 80% 20% t r t f v od nqxx qxx where x = bank a, b, c or d nqxx qxx where x = bank a, b, c or d
idt8t79s818a-08nlgi revision b july 11, 2013 13 ?2013 integrated device technology, inc. IDT8T79S818I-08 data sheet 1-to-8 differential to universal output, clock divider/fanout buffer parameter measurement in formation, continued offset voltage setup differential output voltage setup applications information recommendations for unused input and output pins i nputs: lvcmos control pins all control pins have internal pull up or pulldown resistors; additional resistance is not required but can be added for additional protection. a 1k ? resistor can be used. outputs: lvpecl outputs all unused lvpecl output pairs c an be left floating. we recommend that there is no trace attached. both sides of the differential output pair should either be left floating or terminated. lvds outputs all unused lvds output pairs can be either left floating or terminated with 100 ? across. if they are left floating, there should be no trace attached. lvcmos outputs the unused lvcmos output can be le ft floating. there should be no trace attached. o u t o u t lv d s dc inp u t ? v o s / v o s v cc 100 o u t o u t dc inp u t v cc lv d s
idt8t79s818a-08nlgi revision b july 11, 2013 14 ?2013 integrated device technology, inc. IDT8T79S818I-08 data sheet 1-to-8 differential to universal output, clock divider/fanout buffer wiring the differential input to accept single-ended levels figure 3 shows how a differential input can be wired to accept single ended levels. the reference voltage v 1 = v cc /2 is generated by the bias resistors r1 and r2. the bypass capacitor (c1) is used to help filter noise on the dc bias. this bias circuit should be located as close to the input pin as possible. the ratio of r1 and r2 might need to be adjusted to position the v 1 in the center of the input voltage swing. for example, if the input clock swing is 2.5v and v cc = 3.3v, r1 and r2 value should be adjusted to set v 1 at 1.25v. the values below are for when both the single ended swing and v cc are at the same voltage. this configuration requires that th e sum of the output impedance of the driver (ro) and the series resistance (rs) equals the transmission line impedance. in addition, match ed termination at the input will attenuate the signal in half. this can be done in one of two ways. first, r3 and r4 in parallel should equal the transmission line impedance. for most 50 : applications, r3 and r4 can be 100 : . the values of the resistors can be in creased to reduce the loading for slower and weaker lvcmos driver. when using single-ended signaling, the noise rejection bene fits of differential signaling are reduced. even though the differential input can handle full rail lvcmos signaling, it is recommended that the amplitude be reduced. the datasheet specifies a lower differential amplitude, however this only applies to differential signals. for single-ended applications, the swing can be larger, however v il cannot be less than -0.3v and v ih cannot be more than v cc + 0.3v. though some of the recommended components might not be used, the pads should be placed in the layout. they can be utilized for debugging purposes. the datasheet specifications are characterized and guaranteed by using a differential signal. rec eiv er + - r4 10 0 r3 10 0 rs zo = 50 ohm ro driv er vcc vcc r2 1k r1 1k c1 0.1uf ro + rs = zo v1 vc c vc c figure 3. recommended schematic for wiring a diff erential input to accept single-ended levels
idt8t79s818a-08nlgi revision b july 11, 2013 15 ?2013 integrated device technology, inc. IDT8T79S818I-08 data sheet 1-to-8 differential to universal output, clock divider/fanout buffer 3.3v lvpecl clock input interface the pclk /npclk accepts lvpecl, lvds and other differential signals. both v swing and v oh must meet the v pp and v cmr input requirements. figures 4a to 4c show interface examples for the pclk/ npclk input driven by the most common driver types. the input interfaces suggested here are examples only. if the driver is from another vendor, use their termination recommendation. please consult with the vendor of the driver component to confirm the driver termination requirements. figure 4a. pclk/npclk input driven by a ? 3.3v lvpecl driver figure 4c. pclk/npclk input driven by a ? 3.3v lvds driver figure 4b. pclk/npclk input driven by a ? 3.3v lvpecl driver with ac couple r3 125 r4 125 r1 84 r2 84 3.3v zo = 50 zo = 50 pclk npclk 3.3v 3.3v lvpecl lvpecl input 3 . 3v r1 1 00 ? s p c l k np c l k 3 . 3v lvpe c l i n p u t zo = 50 ? ?
idt8t79s818a-08nlgi revision b july 11, 2013 16 ?2013 integrated device technology, inc. IDT8T79S818I-08 data sheet 1-to-8 differential to universal output, clock divider/fanout buffer 2.5v lvpecl clock input interface the pclk /npclk accepts lvpecl, lvds and other differential signals. both v swing and v oh must meet the v pp and v cmr input requirements. figures 5a to 5c show interface examples for the pclk/ npclk input driven by the most common driver types. the input interfaces suggested here are examples only. if the driver is from another vendor, use their termination recommendation. please consult with the vendor of the driver component to confirm the driver termination requirements. figure 5a. pclk/npclk input driven by a ? 2.5v lvpecl driver figure 5c. pclk/npclk input driven by a ? 2.5v lvds driver figure 5b. pclk/npclk input driven by a ? 2.5v lvpecl driver with ac couple 2. 5v p c l k np c l k 2. 5v 2. 5v lvpe cl lvpecl in p u t
idt8t79s818a-08nlgi revision b july 11, 2013 17 ?2013 integrated device technology, inc. IDT8T79S818I-08 data sheet 1-to-8 differential to universal output, clock divider/fanout buffer lvds driver termination for a general lvds interface, the recommended value for the termination impedance (z t ) is between 90 : and 132 : . the actual value should be selected to match the differential impedance (z 0 ) of your transmission line. a typical point-to-point lvds design uses a 100 : parallel resistor at the receiver and a 100 : differential transmission-line environment. in order to avoid any transmission-line reflection issues, the components should be surface mounted and must be placed as close to the receiver as possible. idt offers a full line of lvds compliant devices with two types of output structures: current source and voltage source. the standard termination schematic as shown in figure 6a can be used with either type of output structure. figure 6b , which can also be used with both output types, is an optional termination with center tap capacitance to help filter comm on mode noise. the capacitor value should be approximately 50pf. if using a non-standard termination, it is recommended to contact idt and confirm if the out put structure is current source or voltage source type. in addition, since these outputs are lvds compatible, the input receiver?s amplitude and common-mode input range should be verified for compatibility with the output. lv d s driver lv d s driver lv d s receiver lv d s receiver z t c z o | z t z o | z t z t 2 z t 2 figure 6a. standard termination figure 6b. optional termination lvds termination
idt8t79s818a-08nlgi revision b july 11, 2013 18 ?2013 integrated device technology, inc. IDT8T79S818I-08 data sheet 1-to-8 differential to universal output, clock divider/fanout buffer termination for 3.3v lvpecl outputs the clock layout topology shown below is a typical termination for lvpecl outputs. the two different layouts mentioned are recommended only as guidelines. the differential outputs are lo w impedance follower outputs that generate ecl/lvpecl compatible out puts. therefore, terminating resistors (dc current path to ground) or current sources must be used for functionality. these outputs are designed to drive 50 ? transmission lines. matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. figures 7a and 7b show two different layouts which are recommended only as guidelines. other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations. figure 7a. 3.3v lvpecl output termination figure 7b. 3.3v lvpecl output termination r1 84 ? r2 84 ? 3.3v r3 125 ? r4 125 ? z o = 50 ? z o = 50 ? lvpecl input 3.3v 3.3v + _
idt8t79s818a-08nlgi revision b july 11, 2013 19 ?2013 integrated device technology, inc. IDT8T79S818I-08 data sheet 1-to-8 differential to universal output, clock divider/fanout buffer termination for 2.5v lvpecl outputs figure 8a and figure 8b show examples of termination for 2.5v lvpecl driver. these terminations are equivalent to terminating 50 ? to v cc ? 2v. for v cc = 2.5v, the v cc ? 2v is very close to ground level. the r3 in figure 8b can be eliminated and the termination is shown in figure 8c. figure 8a. 2.5v lvpecl driver termination example figure 8c. 2.5v lvpecl driver termination example figure 8b. 2.5v lvpecl driver termination example 2.5v lvpecl driver v cc = 2.5v 2.5v 2.5v 50 50 r1 250 r3 250 r2 62.5 r4 62.5 + ? 2.5v lvpecl driver v cc = 2.5v 2.5v 50 50 r1 50 r2 50 + ? 2.5v lvpecl driver v cc = 2.5v 2.5v 50 50 r1 50 r2 50 r3 18 + ?
idt8t79s818a-08nlgi revision b july 11, 2013 20 ?2013 integrated device technology, inc. IDT8T79S818I-08 data sheet 1-to-8 differential to universal output, clock divider/fanout buffer vfqfn epad thermal release path in order to maximize both the removal of heat from the package and the electrical performance, a land pattern must be incorporated on the printed circuit board (pcb) within the footprint of the package corresponding to the exposed metal pad or exposed heat slug on the package, as shown in figure 9. the solderable area on the pcb, as defined by the solder mask, should be at least the same size/shape as the exposed pad/slug area on the package to maximize the thermal/electrical performance. sufficient clearance should be designed on the pcb between the outer edges of the land pattern and the inner edges of pad pattern for the leads to avoid any shorts. while the land pattern on the pcb provides a means of heat transfer and electrical grounding from the package to the board through a solder joint, thermal vias are nece ssary to effectively conduct from the surface of the pcb to the gro und plane(s). the land pattern must be connected to ground through thes e vias. the vias act as ?heat pipes?. the number of vias (i.e. ?h eat pipes?) are application specific and dependent upon the package power dissipation as well as electrical conductivity requiremen ts. thus, thermal and electrical analysis and/or testing are recommended to determine the minimum number needed. maximum thermal and electrical performance is achieved when an array of vias is incorporated in the land pattern. it is recommended to use as many vias connected to ground as possible. it is also recommended t hat the via diameter should be 12 to 13mils (0.30 to 0.33mm) with 1oz copper via barrel plating. this is desirable to avoid any solder wicking inside the via during the soldering process which may result in voids in solder between the exposed pad/slug and the thermal la nd. precautions should be taken to eliminate any solder voids between the exposed heat slug and the land pattern. note: these recommendations are to be used as a guideline only. for further information, please refer to the application note on the surface mount assembly of amkor?s thermally/ electrically enhance leadframe base package, amkor technology. figure 9. p.c. assembly for exposed pad thermal release path ? side view (drawing not to scale) solder solder pin pin exposed heat slug pin pad pin pad ground plane land pattern (ground pad) thermal via
idt8t79s818a-08nlgi revision b july 11, 2013 21 ?2013 integrated device technology, inc. IDT8T79S818I-08 data sheet 1-to-8 differential to universal output, clock divider/fanout buffer power considerations a forced airflow has to be guaranteed in order to meet the thermal requirements of the part at 3.3v 5%. ? no flow is required at 2.5v 5%. table 6. minimum recommended air flow conditions lvds power considerations this section provides information on power dissipation and junc tion temperature for the idt8t79s 818i-08. equations and example calculations are also provided. 1. power dissipation. the total power dissipation for the IDT8T79S818I-08 is the su m of the core power plus the power dissipated into the load. ? the following is the power dissipation for v cc = 3.3v + 5% = 3.465v, which gives worst case results. note: the maximum i cc current at 85 c is 269ma. ? power (core) max = v cc_max * i cc_max = 3.465v * 269ma = 932.1mw 2. junction temperature. junction temperature, tj, is the temperatur e at the junction of the bond wire and bo nd pad directly affects the reliability of the device. the maximum recommended junction temperature is 125c. limiting the in ternal transistor junction temperature, tj, to 125c ensures that the bond wire and bond pad temperature remains below 125c. the equation for tj is as follows: tj = ? ja * pd_total + t a tj = junction temperature ? ja = junction-to-ambient thermal resistance pd_total = total device power dissipation (example calculation is in section 1 above) t a = ambient temperature in order to calculate junction temperature, the app ropriate junction-to-ambient thermal resistance ? ja must be used. assuming 1m/s air flow and a multi-layer board, the appropriate value is 42c/w per table 7a below. therefore, tj for an ambient temperature of 85c with all outputs switching is: 85c + 0.9321w * 42c/w = 124.2c. this is below the limit of 125c. this calculation is only an example. tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of board (multi-layer). table 7a. thermal resistance ? ja for 32-lead vfqfn package power supply voltage ( v cc, volts) minimum airflow minimum typical maximu m meters per second 2.375 2.5 2.625 0 3.135 3.3 3.465 1 ? ja by velocity meters per second 012 multi-layer pcb, jedec standard te st boards 48.9c/w 42c/w 39.4c/w
idt8t79s818a-08nlgi revision b july 11, 2013 22 ?2013 integrated device technology, inc. IDT8T79S818I-08 data sheet 1-to-8 differential to universal output, clock divider/fanout buffer lvpecl power considerations this section provides information on power dissipation and juncti on temperature for the idt8t79s 818i-08, for all outputs that a re configured to lvpecl. equations and example calculations are also provided. 1. power dissipation. the total power dissipation for the IDT8T79S818I-08 is the sum of the core power plus the power dissipated due to the load. ? the following is the power dissipation for v cc = 3.3v + 5% = 3.465v, which gives worst case results. note: please refer to section 3 for details on calculating power dissipated due to the load. ? power (core) max = v dd_max * i ee_max = 3.465v * 175ma = 606.4mw ? power (outputs) max = 31.6mw/loaded output pair ? if all outputs are loaded, the total power is 8 * 31.6mw = 253mw total power_ max (3.465v, with all outputs s witching) = 606.4mw + 253mw = 860mw 2. junction temperature. junction temperature, tj, is the temperatur e at the junction of the bond wire and bo nd pad directly affects the reliability of the device. the maximum recommended junction temperature is 125c. limiting the in ternal transistor junction temperature, tj, to 125c ensures that the bond wire and bond pad temperature remains below 125c. the equation for tj is as follows: tj = ? ja * pd_total + t a tj = junction temperature ? ja = junction-to-ambient thermal resistance pd_total = total device power dissipation (example calculation is in section 1 above) t a = ambient temperature in order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance ? ja must be used. assuming one meter per second and a multi-layer board, the approp riate value is 42c/w per table 7b below. therefore, tj for an ambient temperature of 85c with all outputs switching is: 85c + 0.860w * 42c/w = 121.2c. this is below the limit of 125c. this calculation is only an example. tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of board (multi-layer). table 7b. thermal resistance ? ja for 32-lead vfqfn package ? ja by velocity meters per second 012 multi-layer pcb, jedec standard te st boards 48.9c/w 42c/w 39.4c/w
idt8t79s818a-08nlgi revision b july 11, 2013 23 ?2013 integrated device technology, inc. IDT8T79S818I-08 data sheet 1-to-8 differential to universal output, clock divider/fanout buffer 3. calculations and equations. the purpose of this section is to calculate the power dissipation fo r the lvpecl output pairs. lvpecl output driver circuit and termination are shown in figure 11. figure 11. lvpecl driver circuit and termination t o calculate power dissipation per output pair due to th e load, use the following equations which assume a 50 ? load, and a termination voltage of v cc ? 2v. ? for logic high, v out = v oh_max = v cc_max ? 0.75v ? (v cc_max ? v oh_max ) = 0.75v ? for logic low, v out = v ol_max = v cc_max ? 1.6v ? (v cc_max ? v ol_max ) = 1.6v pd_h is power dissipation when the output drives high. pd_l is the power dissipation when the output drives low. pd_h = [(v oh_max ? (v cc_max ? 2v))/r l ] * (v cc_max ? v oh_max ) = [(2v ? (v cc_max ? v oh_max ))/r l ] * (v cc_max ? v oh_max ) = ? [(2v ? 0.75v)/50 ? ] * 0.75v = 18.8mw pd_l = [(v ol_max ? (v cc_max ? 2v))/r l ] * (v cc_max ? v ol_max ) = [(2v ? (v cc_max ? v ol_max ))/r l ] * (v cc_max ? v ol_max ) = ? [(2v ? 1.6v)/50 ? ] * 1.6v = 12.8mw total power dissipation per output pair = pd_h + pd_l = 31.6mw v out v cc v cc - 2v q1 rl
idt8t79s818a-08nlgi revision b july 11, 2013 24 ?2013 integrated device technology, inc. IDT8T79S818I-08 data sheet 1-to-8 differential to universal output, clock divider/fanout buffer reliability information table 8. ? ja vs. air flow table for a 32-lead vfqfn package transistor count the transistor count for IDT8T79S818I-08 is: 2618 ? ja vs. air flow meters per second 012 multi-layer pcb, jedec standard te st boards 48.9c/w 42.0c/w 39.4c/w
idt8t79s818a-08nlgi revision b july 11, 2013 25 ?2013 integrated device technology, inc. IDT8T79S818I-08 data sheet 1-to-8 differential to universal output, clock divider/fanout buffer 32 lead vfqfn package out line and package dimensions
idt8t79s818a-08nlgi revision b july 11, 2013 26 ?2013 integrated device technology, inc. IDT8T79S818I-08 data sheet 1-to-8 differential to universal output, clock divider/fanout buffer ordering information table 9. ordering information part/order number marking package shipping packaging temperature 8t79s818a-08nlgi idt8t79s818a-08nlgi ?lead-free? 32 lead vfqfn tray -40 ? c to 85 ? c 8t79s818a-08nlgi8 idt8t79s818a-08nlgi ?lea d-free? 32 lead vfqfn tape & reel -40 ? c to 85 ? c
idt8t79s818a-08nlgi revision b july 11, 2013 27 ?2013 integrated device technology, inc. IDT8T79S818I-08 data sheet 1-to-8 differential to universal output, clock divider/fanout buffer revision history sheet rev table page description of change date b 1 15 16 features section - deleted cml levles from the pclk bullet. 3.3v lvpecl clock input interface application note - deleted cml references. 2.5v lvpecl clock input interface application note - deleted cml references. 7/11/13
IDT8T79S818I-08 data sheet 1-to-8 differential to universal output, clock divider/fanout buffer disclaimer integrated device technology, inc. (idt) and its subsidiaries reserve the ri ght to modify the products and/or specif ications described herein at any time and at idt? s sole discretion. all information in this document, including descriptions of product features and performance, is s ubject to change without notice. performance specifications and the operating parameters of the described products ar e determined in the independent state and are not guaranteed to perform the same way when in stalled in customer products. the informa tion contained herein is provided without re presentation or warranty of any kind, whether express or implied, including, but not limited to, the suitability of idt?s products for any partic ular purpose, an implied warranty of merc hantability, or non-infringement of the in tellectual property rights of others. this document is presented only as a gui de and does not convey any license under intellectual property rights of idt or any third parties. idt?s products are not intended for use in applications involving extreme environmenta l conditions or in life support systems o r similar devices where the failure or malfunction of an idt product can be reasonably expected to signifi- cantly affect the health or safety of users. anyone using an id t product in such a manner does so at their own risk, absent an express, written agreement by idt. integrated device technology, idt and the idt logo are registered tr ademarks of idt. other trademarks and service marks used he rein, including protected names, logos and designs, are the property of idt or their respective third party owners. copyright 2013. all rights reserved. 6024 silver creek valley road san jose, california 95138 sales 800-345-7015 (inside usa) +408-284-8200 (outside usa) fax: 408-284-2775 www.idt.com/go/contact idt technical support netcom@idt.com +480-763-2056 we?ve got your timing solution

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